As a senior member of the High Speed Serial IO design team in Intel's Server CPU Development Group.
You will be responsible for:
Design target high frequencies.
Require a tightly coupled interface to the backbone of complex blocks within the uncore sub-system as well as to the analog front end.
Chip in to definition of the validation flows, proposing creative solutions for logic block validation.
Work with circuit designers to support AMS validation.
Your responsibilities will include, but not be limited to:
Authoring validation plans
Define the needs of tools and methodology to ensure high quality Silicon, coding validation test cases using UVM/OVM techniques
Chip in to functional and performance validation
You will also be involved with test bench creation, participating in silicon debug, and leading a small team of engineers in many of the above activities.
You would also work in a very collaborative environment and would have to work well with engineers from other design disciplines and from peer projects across sites.
You will have a BS/MS degree in Electrical Engineering, Computer Engineering or Computer Science.
You will have 12+ years of experience in:
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.