Job Description Oversees definition, design, verification, and documentation for SoC System on a Chip development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.
Looking for game changers who can help us to create world class product !!Be the part of DFT CoE. Let's create together Best In Class DFT Solutions to achieve single digit DPPM. Eligibility criteria : Candidate should possess a Bachelors or Master's degree in Computer/ Electrical/Electronic Engineering with 9+ years' experience. Strong hands on knowledge of DFT architecture, design, methodologies and tools - Scan, MBIST, Analog DFT, JTAG, Security. Had executed/experienced complete SOC DFT cycle for at least 5 SOCs. Excellent scripting, debug & analytic skills. Ability to provide technical guidance to junior folks in team. A good team player with excellent interpersonal and communication skills.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.