Analysis, interpretation, and assessment of hardware architectural specifications defining feature requirements for 3D Graphics blocks.
Definition and development of microarchitecture specifications, logic designs, and HDL code for 3D Graphics blocks.
Design implementations must meet functional and performance requirements, physical/structural design constraints timing, area, power, as well as proprietary design rules and other quality criteria.-
Definition and development of test plans, verification environments, validation components bus functional models, trackers, checkers, scoreboards, test benches, etc., functional coverage points, assertions, random and directed tests, random test constraints, etc. to validate 3D Graphics blocks at various levels of integration.
Integration and maintenance of HDL models and verification environments for simulation and ASIC logic synthesis.
Execution and debug of hardware simulations achievement of functional test coverage objectives.
Identification and closure of design and environment defects, including bug fixes requiring manual ECOs gate-level netlist edits.
Characterization and analysis of performance and power results implementation of corresponding design modifications and optimizations as required to achieve power and performance targets.
Execution of ASIC logic synthesis flows implementation of corresponding design modifications and optimizations as needed to achieve timing and area objectives.
Debug of graphics hardware in emulation and/or silicon hardware environments working with synthetic low-level tests as well as with stimulus from real-world applications and benchmarks and the graphics driver.
BS Degree in Electrical Engineering, Computer Engineering, or other related field
3+ years of relevant experience with a Bachelor's Degree, OR 2+ years with Masters
Working knowledge of computer architecture/organization fundamentals
Experience/proficiency in front-end logic design and verification of large (aprox. 100Ks to Ms) of gates, complex, high-speed ~1GHz digital systems, under real-world physical design constraints
Experience/proficiency in logic design implementation and verification using coding in hardware description RTL and verification languages (such as Verilog or System Verilog applying good coding style)
Experience/proficiency in usage/execution of logic simulation, synthesis, and timing analysis tools and environments familiarity with broader ASIC development flows hardware/hardware model debug
Experience/proficiency in programming or scripting languages (such as C/C++, Perl, Ruby, and Python)
Familiarity with 3D Graphics architecture concepts, APIs, and standards - e.g., Direct3D, OpenGL media/video codec standards implementation of vector-based DSP/SIMD algorithms Intel CPU architecture
Knowledge of coverage-based validation concepts and application - functional coverage points, assertions, random and directed tests, random test constraints, etc. using System Verilog or similar verification languages/tools UVM/OVM verification methods
Experience with Synopsys ASIC design tools - VCS simulator, Design Compiler, IC Compiler- Familiarity with formal verification methods - formal property verification e.g., Jasper, high-level/algorithmic formal equivalence checking e.g., HECTOR
Familiarity with digital hardware emulation and hardware debug tools - emulators, logic analyzers, etc.
Experience/proficiency in definition and development/implementation of test plans, verification simulation environments, validation components, and tests
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.