We are an end-to-end design team based in Bangalore part of Intel Labs. In this position, you will be responsible for the back-end design tasks and support design implementation and integration including Logic synthesis, Layout & Floor planning and full chip timing roll-up. In this position, your responsibilities will include the following: - Working closely with the Design and Micro-Arch team in studying, understanding, analyzing the micro-arch specifications and own Partition/Block level, IP level layout. - Interacting with micro-architects and the design team in areas of Logic synthesis, Layout methodology development, and Performance/Layout verification to ensure that layout goals are met. - Participating in Partition and IP floor-planning and implementing the physical layout for the IP. - Verifying and ensuring that Area/Power/Performance specifications are met. - Ownership of synthesis in order to estimate power and timing constraints at IP, partition and full chip level - Own IP block level floor planning, APR and timing closures - Setup project design environment and tool flow setup and development.
You should possess a Master's degree in EE with at least 4 years of experience or a Bachelor's degree in EE with at least 5 years of experience in VLSI physical design. Additional qualifications include: - Knowledge of microelectronics designs, semiconductor device physics, CMOS process and physical layout - Good hands-on Knowledge on EDA tools like Synopsys design tools in the field of logic and physical design. - Experience in STA, LEC-Formal verification, Redhawk IR-drop analysis and low power verification would be a plus.- Good knowledge in scripting languages specially in Perl*, Tcl* and Shell csh/tcsh/bash scripting would be a plus. Hands-on experience in converging complex blocks from RTL to GDSII 100K-1 million gates with embedded black-boxes. - Strong background in converging power, timing and functional equivalence is required. - Exposure to handling APR blocks associated with Analog IP's like DDR and PCIe would be a plus - Experience in design automation for design methodology and flow development.Inside this Business Group
Intel Labs is the company's world-class, industry leading research organization, responsible for driving Intel's technology pipeline and creating new opportunities. The mission of Intel Labs is to deliver breakthrough technologies to fuel Intel's growth. This includes identifying and exploring compelling new technologies and high risk opportunities ahead of business unit investment and demonstrating first-to-market technologies and innovative new usages for computing technology. Intel Labs engages the leading thinkers in academia and industry in addition to partnering closely with Intel business units.