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Job ID: JR0053501
Job Category: Engineering
Primary Location: Folsom, CA US
Other Locations:
Job Type: Experienced Hire

Graphics Hardware Design Engineer

Job Description

If you're interested in computer graphics and working with leading graphics hardware engineers on Intel's latest GPU/CPU architecture, then our Visual and Parallel Computing Group VPG has opportunities for you. VPG delivers Intel's 3D graphics, media, display, GPU, and Parallel Computing Technology. This position is in 3D Graphics hardware front-end development where you will be working closely within a team of graphics hardware design/validation engineers, microarchitects, and architects on 3D Graphics blocks subsystems targeting a wide range of Intel's future generation processor products. Our development environment is dynamic and fast-moving, focused on high-quality results, frequently entailing multiple projects under concurrent development. You will be encouraged to take informed risks, to continuously seek useful design innovations and process improvements, and to have fun while doing so. This position you will be collaborating with team members and other key partners located across multiple US and international sites.

Behavioral traits include:

  • Strong communication, interpersonal, and problem solving skills
  • Strong technical and business writing skills
  • Motivation, self-direction, and ability to work effectively both independently and as part of a diverse cross-geographic team
  • Ability and willingness to efficiently manage multiple concurrent assignments, to deal with dynamic objectives and plans, and to deliver high-quality output against deadlines

Responsibilities include:

  • Analysis, interpretation, and assessment of hardware architectural specifications defining feature requirements for 3D Graphics blocks.
  • Definition and development of microarchitecture specifications, logic designs, and RTL code for 3D Graphics blocks that meet functional, performance, timing and area constraints.
  • Definition and development of test plans, verification environments, validation components, trackers, checkers, scoreboards, test benches to validate 3D Graphics blocks at various levels of integration.
  • Execution of ASIC logic synthesis flows implementation of corresponding design modifications and optimizations as needed to achieve timing and area objectives.


Qualifications

BS in Electrical and/or Computer Engineering, plus 3+ years of relevant post-degree experience.  MS is preferred. 

You must have 3+ years of training, experience, and demonstrable proficiency in:

  • Computer architecture/organization fundamentals
  • Front-end logic design and verification of large 100Ks to Ms of gates, complex, high-speed ~1GHz digital systems, under real-world physical design constraints
  • Logic design implementation and verification using coding in hardware description RTL and verification languages such as Verilog or System Verilog applying good coding style
  • Definition and development/implementation of test plans, verification simulation environments, validation components, and tests
  • Usage/execution of logic simulation, synthesis, and timing analysis tools and environments familiarity with broader ASIC development flows hardware/hardware model debug
  • Unix and Windows OS usage
  • Programming or scripting languages such as C/C++, Perl, Ruby, and Python

Preferred qualifications/skills include training, experience, and demonstrable proficiency in:

  • 3D Graphics architecture concepts, APIs, and standards - e.g., Direct3D, OpenGL media/video codec standards implementation of vector-based DSP/SIMD algorithms Intel CPU architecture
  • Coverage-based validation concepts and application - functional coverage points, assertions, random and directed tests, random test constraints, etc. using System Verilog or similar verification languages/tools UVM/OVM verification methods
  • Synopsys ASIC design tools - VCS simulator, Design Compiler, IC Compiler
  • Formal verification methods - formal property verification e.g., Jasper, high-level/algorithmic formal equivalence checking e.g., HECTOR
  • Familiarity with digital hardware emulation and hardware debug tools - emulators, logic analyzers, etc.

Does this describe you? Then we encourage you to apply for this opportunity.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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