To work on next generation i7/i9 processor, on 10nm and 7nm technology, and work on next generation of mix-process node integration technology to enable various computing accelerator integration, in the era of hyper scale computing.Responsible to validate and integrate third party Intellectual Properties IPs ensuring they meet product specification and functionality before they are productized into physical chip. Required to work very closely with design teams and architects to implement the low-level Register Transfer Logic RTL design to ensure overall good functionality of the chip. Develop specific test environment/platform, validation methodology and test plan to validate System on Chip SOC design by identifying and exercising boundary conditions and special cases in an effort to "break" the chip to find that last elusive bug.
Bachelor degree or Master in Electrical and Electronics, Computer Engineering or Computer Science with at least 5 years of relevant experience in System on Chip SOC design and validation experiences.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.