This is an Intel contract employee ICE position with a contract employment period of 12 months with no relocation package or permanent visa sponsorship available. As a Power Delivery Physical Design Engineer, you would be responsible for creating bottoms-up elements of chip design including but not limited to FET, cell, and block-level custom layouts, FUB-level floor plans, abstract view generation, RC extraction and schematic-to-layout verification. You will also be responsible for full chip floor planning, integration and handling of full chip issues including Antenna, Latch-Up, ESD, drcd and density and getting a database ready for tape out.
In addition, you would be responsible for:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through relevant previous jobs and/or research experiences.
Intel Labs is the company's world-class, industry leading research organization, responsible for driving Intel's technology pipeline and creating new opportunities. The mission of Intel Labs is to deliver breakthrough technologies to fuel Intel's growth. This includes identifying and exploring compelling new technologies and high risk opportunities ahead of business unit investment and demonstrating first-to-market technologies and innovative new usages for computing technology. Intel Labs engages the leading thinkers in academia and industry in addition to partnering closely with Intel business units.