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Job ID: JR0052330
Job Category: Contract Employee
Primary Location: Hillsboro, OR US
Other Locations:
Job Type: Intel Contract Employee

Power Delivery Physical Design Engineer – Intel Co

Job Description

This is an Intel contract employee ICE position with a contract employment period of 12 months with no relocation package or permanent visa sponsorship available. As a Power Delivery Physical Design Engineer, you would be responsible for creating bottoms-up elements of chip design including but not limited to FET, cell, and block-level custom layouts, FUB-level floor plans, abstract view generation, RC extraction and schematic-to-layout verification. You will also be responsible for full chip floor planning, integration and handling of full chip issues including Antenna, Latch-Up, ESD, drcd and density and getting a database ready for tape out.

In addition, you would be responsible for:

  • Troubleshooting a wide variety up to and including difficult design issues and applied proactive intervention- Scheduling, coordinating and executing complex chips development and working with many MDs and PDEs to execute flawlessly to adhere to tape-in milestones
  • Knowledge of Auto Place and Route tools and associated integration of soft and hard IPs will be a PLUS
  • Knowledge of circuit design and helping designers modify schematics as required for layout and running parasitic and extracted simulations of key analog blocks will be a PLUS


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through relevant previous jobs and/or research experiences.

Minimum qualifications

  • Must have a BS, MS or PhD in Electrical Engineering, Computer Engineering or related discipline or in lieu of a degree, a minimum of 7 years of Analog IC circuit physical design experience
  • Minimum 5 years of custom analog integrated circuit physical design experience including experience in both Cadence design flow and Intel's Genesis tool
  • Experience with foundry technology in 180nm, 65nm, 28nm and 16FF nodes
  • Knowledge of layout of power management blocks such as power FETs, amplifiers, comparators, inductors, capacitors, transformers and other passive devices
  • Must understand how to run extraction tools and how to use that feedback to guide physical design

Preferred qualifications

  • Experience with Intel's advanced technology nodes

Inside this Business Group

Intel Labs is the company's world-class, industry leading research organization, responsible for driving Intel's technology pipeline and creating new opportunities. The mission of Intel Labs is to deliver breakthrough technologies to fuel Intel's growth. This includes identifying and exploring compelling new technologies and high risk opportunities ahead of business unit investment and demonstrating first-to-market technologies and innovative new usages for computing technology. Intel Labs engages the leading thinkers in academia and industry in addition to partnering closely with Intel business units.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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