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Job ID: JR0052142
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

SoC Design Engineer

Job Description
Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and sub-systems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.


Qualifications

Job Requirement: In this position, you will be responsible for all aspects of STA & timing closure activities of Intel's SoCs in lower technology nodes. Your tasks will include but not limited to:Design & Architecture understanding, Interaction with FE/DFT/Verification teams, Clocking, Constraints development, ACIO Timing, Understanding on synchronous & asynchronous paths, Clock domain crossing issues, Understanding and debugging extraction issues, Deciding timing signoff modes & corners, Design margins, Hierarchical timing including IO budgeting for partitions, Drive the designs to timing closure, interacting/supporting synthesis and APR team during timing closure cycle, timing ECOs, Timing model build, Timing signoff & quality checks. You will also be part of debug/troubleshoots for a wide variety of tasks up to and including difficult/critical design issues and proactive intervention, as required.Qualification: Education: B.Tech. or M.Tech. in Electrical/Electronics Engineering with 4 to 9 years' of experience. Preference: Master's Degree in Electrical/Electronics Engineering with VLSI/microelectronics specialization, with 4 to 9 years of experience in STA.Key Skills: - In-depth knowledge & hands-on experience with the overall silicon implementation flows and methodologies such a STA, Synthesis, Clocking is required. Good understanding & exposure of overall Timing closure cycle in SoC. - Good scripting skills in TCL/Perl/Shell. Expertise in STA signoff tools PT/ETS. - Skill in Synopsys tools PT/DC & exposure to ICC will be an added advantage. - Solid understanding of process and design interactions as they relate to target frequency and interaction with timing paths and resulting leakage and power trade-offs. - Solid technical and good communication skills.- Good team player ​

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


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