Responsible for delivering IP and Sub-IP blocks for critical Networking Products manufactured on leading edge process technologies using the latest design methodologies.Responsibilities will include but not limited to:Driving the Physical Design convergence flows on RTL 2 GDS multiple sub-IP and IP blocks.Understanding, validating and deploying new tools and solutions in multiple Digital VLSI domain like FEV, Timing, Place and RouteAnalyze, debug and develop solutions for convergence challenges to meet design metrics like area, power and performance
Inside this Business Group
A Bachelor or Masters of Engineering degree in Electrical/ Electronic Engineering/ VLSI Engineering.6 or more years of hands-on experience in physical design convergence from logic synthesis to layout verification.Knowledge of few of Industry standard EDA tool like Design Complier, Descartes, ICC, ICC2, Primetime, Red hawk and Formality Excellent understanding of digital design and circuit theoryExpertise in scripting languages like Perl and/or Tcl
The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.