You will be part of the R&D team chartered to deliver IP and subsystem design to SOC team across Intel for latest products ranging from server, desktop, tablet, to IOT and wearables. Your responsibilities include:
-Working closely with silicon architect and designer, influencing design definition and implementation.
-Defining and developing testbench, enhancing verification flow and methodologies for validation environment.
-Developing verification collaterals such as scoreboard, behavioral model, tracker/checker, automated tools for the validation needs.
-Validating the functionality of RTL design by developing testplan, tests sequences, coverage point or test tools.
Inside this Business Group
-The applicant should possess Bachelor degree in Electrical & Electronics or Computer System or related Engineering or higher, and 5+ years of Pre-Silicon Validation experience. -Experience in System Verilog, OVM/UVM, RTL model build or testbench development. -Capable in developing testplan, tests contents and coverage points for validation purpose based on High Level Architecture spec. -Experience in VLSI or Structural and Physical design flow/methodology. -Strong programming skill in Perl, C++, Tcl and etc -Strong analytical and debugging skill, and creative in problem solving. -Good leadership, interpersonal and communication skills.
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.