You will be part of the R&D team chartered to deliver IP and subsystem design to SOC team across Intel for latest products ranging from server, desktop, tablet, to IOT and wearables. Your responsibilities include:
-Participate in the development of Architecture and Microarchitecture specifications for the Logic components.
-Working closely with silicon architect and micro-architect in design definition and implementation.
-Provides IP integration support to SoC customers and represents RTL team.
-Work closely with Validation Architect in defining validation strategy and reviewing testplan
Inside this Business Group
The applicant should possess -Bachelor degree in Electrical & Electronics or Computer System or related Engineering or higher, and 5+ years of RTL Logic design experience. -Experience in System Verilog, OVM/UVM, RTL development for high performance and low power design. -Well verse in interface timing budget, clock domain crossing design, and high speed IO protocol, such as PCIe or SATA. -Experience in VLSI or Structural and Physical design flow/methodology. -Strong programming skill in Perl, C++, Tcl and etc -Strong analytical and debugging skill, and creative in problem solving. -Good leadership, interpersonal and communication skills.
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.