Creates bottoms-up elements of Server, Networking, and Emerging Data Center SOC design including but not limited to synthesis, partition level floorplan, abstract view generation, RC extraction and schematic-to-layout verification and debug using phases of physical design development including parasitic extraction, static timing, reliability analysis, clock generation, custom polygon editing, auto-place and route algorithms, floor planning, full-chip assembly, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design. Innovation and efficiency improvement in the day to day execution is an added expectation.
Inside this Business Group
You should possess a Bachelor/Masters of Science degree in Electronic or Electrical Engineering. You should have 3-6 years of working experience in structural physical design or related field. Additional qualifications include: - Knowledge of silicon design- Knowledge and experience in structural physical design - Strong programming skills in Perl and TCL - Good communication and strong analytical skills - Strong team player - Knowledgeable in 5G, networking architecture, and hardware design would be an added advantage
The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.