Apply Now    
Job ID: JR0051676
Job Category: Engineering
Primary Location: Haifa, IL
Other Locations: Israel, Yakum
Job Type: Experienced Hire

DFx design/validation engineer for CDG- Yakum/Haifa

Job Description

We have a challenging position as a DFx design/validation engineer for CDG (Client Development Group) CPU design team. You will be part of the DFx team (Design for testability DFT, manufacturability DFM, debug DFD and validation DFV) and will have an opportunity to influence the way our future CPUs will be tested, validated, and debugged.

In this position you will take part in design and validation of DFx features in one of our future CPUs. Responsibilities will include one or more of the following:

  • Participation in definition of DFx solutions for future test/debug/validation needs.
  • Logic design of DFx units and global debug features within the processor.
  • Logic validation of DFx features at various hierarchy levels.

#Verification #HWatIntel

#ComputeCommunityISR
#ComputeHWISR

#juniorexperienceISR
#HWjuniorexperienceISR 


Qualifications

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.



Other Locations

Israel, Yakum

Apply Now    

What would you like to do now?

Connect with Us

Get Job Alerts

Get started
Student Center

Find out more about working at Intel

Learn more
Education

Jobs@Intel Blog

Learn more

Grow your network of opportunities