In this role, candidate will be responsible for Back-End implementation of different IPs. This includes resolving the issues i On Logic synthesis, FEV, Block level floor-planning, ii Multi-power domain complexities, iii Place & Route, quality fixes & low power checks iv Clock tree synthesis complexities like balancing the clocks between multiple clocks v LVS & DRC cleanup, vi timing closure
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.