Job Description In this position, candidate will be responsible for developing flows to perform Static Timing Analysis STA for Full Chip of Intel CPU design. Responsibilities will be included but not limited to 1. Owning the full chip timing, interconnect, netlist tools and flows 2. Developing timing methodologies for efficiency in design convergence 3. Performing Full Chip interconnect analysis and providing repeater methodology and solutions. 4. Working across domains, sites and organization to achieve faster full chip timing convergence.
-Should possesses a Master's Degree in VLSI with minimum 6 Yrs experience-should have good understanding of static timing analysis and latch based design. -should have understanding of hierarchical timing analysis. -should have knowledge in scripting languages - Perl, TCL-Knowledge of vendor's tool PrimeTime and ILM/ETM/HyperScale will be added advantage
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.