As a Digital Design Engineer you will be responsible for developing RTL for SERDES digital control and SerDes testchip. Developing RTL for protocol-specific PCS such as PCIe, USB3.0, etc. Collaborating with analog design and system team to develop SerDes control algorithm.
In addition, you will develop FPGA interop platform for SerDes validation. Collaborate with digital verification team in order to produce high quality digital solutions. Post-Silicon bring-up support for characterization lab and ATE Front-end integration support with IP customers.
You will also exhibit the following behaviors:
You must possess the below minimum qualifications to be initially considered for this position. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.
Additional Preferred Qualifications:
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.