Sound understanding of functional verification fundamentals encompassing state machine verification, complex protocol verification, functional test strategies, directed and stress test generation, verification infrastructures and verification and/or debug flows - Gate level simulations - Adept in programming and/or scripting C++, Perl* and others and be conversant with flows and tools for VLSI logic design and/or functional verification - Excellent written and verbal communication skills - Person in this role is expected to lead the verification activity at cluster level as well as Full Chip, SOC level - Good knowledge on functional and code coverage - Drive the overall verification methodology using HVLs like system Verilog The following qualifications would be added advantages: - In depth knowledge of System Verilog and verification methodologies like OVM Working experience on the PCIe, SATA, OCP, UART-Working knowledge of modern PC architecture Specific IO architecture knowledge is a plus - Extensive knowledge of System Verilog and working knowledge of verification methodologies like OVM and others.
You should possess a Bachelor's and/or a Master's degree in Electronics and/or Electronics and Communication and/or Very Large Scale Integration VLSI area. Additional qualifications include:- More than 10+ years of VLSI Front-end experienceInside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.