Job Description Able to independently develop micro-architecture and RTL design based on high level Hardware Architecture Specifications of IPs in networking domain. Develop local block level test bench and validate the RTL code for correct functionalityAssist Pre-Silicon Verification team in developing Test plan and test coverage. Review the coverage reports from regression tests and provide feedback to verification team. Provide debug support in triaging test failures. Collaborate with system validation and software teams for platform level debug.Work with structural design team to close floorplan and static timing on the blocks designed by youGeneric description:Performs logic design, Register Transfer Level RTL coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs. Participates in the development of Architecture and Microarchitecture specifications for the Logic components. Provides IP integration support to SoC customers and represents RTL team.
Qualifications:Bachelor of Engineering with 12+ years of experience/Master of Engineering with 10+ years of relevant experience in Digital design and VLSI domainExperience in networking is preferredMust have years of hands on experience in Verilog/VHDL/System Verilog and simulation toolsKnowledge in formal validation and assertion based methodology is plusExcellent communication and interpersonal skills
Inside this Business Group
The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.