As a Pre/Post Silicon Validation Engineer, you are required to creates, defines and develops system validation environment & test suites. Uses & applies emulation & platform-level tools & techniques to ensure performance to spec. You are responsible for the development of methodologies, execution of validation plans, and debug of failures. Requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Pre-silicon Validation teams in improving post-silicon test content and providing feedback for future on-die debug features.You are responsible in validating the functionality of new architectural features of next generation designs by developing test plans, tests content, coverage points or test tools.You are focal point between a number of Architecture, Design and Validation teams within Intel and across different sites.
Solid understanding and experience in any of the following architecture:
oPower Management architecture who familiar in PMC feature, VID setting, Gate/Chip level power management transition state & etc.
oMemory architecture who familiar in Cache/Memory structure, Memory to CPU ALU/CC transition state, Memory Mapping & etc.
oUSB architecture who familiar in USB Bulk/Interrupt/Isochronous transfer, Type of USB, Host/Device relationship, Transmission & etc.
oPCIe architecture who familiar in PCIe interconnect, link, Lane, Configuration, Interrupt, I/O Read/Write, PCIe Layer, Form Factor & etc.
oWiFi/GPS/Bluetooth/RF architecture who familiar in Wireless LLC characteristic, Data transition, I/O Read Write, Authentication, RF transmission & etc.
oStorage architecture who familiar in eMMC/SD Card/UFS/HDD Data transfer, I/O Read Write, DMA, & etc.
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.