Responsibilities include: - Front end RTL design and validation of state of the art graphics functional blocks. - Expertise in micro architecture preferably in the power management, clocking, micro controllers- Validation Environment development - Creating and developing validation test plans and test scenarios to prove the correctness of the design - Development of validation components for a simulation-based environment, bus functional models, trackers, checkers, scoreboards, and test benches - Building and delivery of an RTL model of the design per micro architecture specification- Development of functional coverage and achieving coverage goals - Identifying and driving to closure of bugs - Developing methodologies and capabilities, and driving process improvements - Working closely with design engineers, micro-architects, and other team members to ensure high quality of test plans, functional coverage, and tests - Ability to deliver high-quality output against deadlines and able to work effectively in a cross-site team environment - Problem-solving, communication, and interpersonal skillsThis team is responsible to ensure the highest quality of the graphics designs, in a dynamic cross-team environment.
Preferred skills and experience
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.