As a member of the VTT Graphics DFx Hardware group, you will be responsible for the following activities:
You will work on the design, RTL/GLS validation, automation, and/or timing analysis in one of the following DFx domains: Controller, Scan, Array DFT, Functional DFT, or DFD
You will also contribute or be involved with trace/pattern generation efforts as well as post-silicon enabling, debug support, and/or analysis of the DFx features/content types you are responsible for.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.