Job Description This position is in Intel's PEG Centralized Design-for-Test team. This team is responsible for driving consistent DFT architecture, methodology, and flows across various product segments. Candidates should be well versed with industry standard DFT techniques such as scan/ATPG, memory Built-in-Self-Test MBIST, Test Access Port TAP, boundary scan, I/O testing, etc. The role also involves supporting multiple design teams and cross functional activities working with debug, post silicon, and bring up teams.
BSEE and 12+ years in Design and DFT or MSEE and 10+ years in DFT. The candidate should be well versed with Scan, ATPG, Memory test, IO testing. The candidate should also have experience in DFT EDA tools, architectures, IP development, vector generation, bring-up of Si to production ramp. The candidate should also have experience in automation of DFT insertion and validation tasks. Understanding of SoC Design Flows, Complexity and Design team needs is required.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.