The Mixed Signal IP Solutions Group MIG within the Platform Engineering Group is looking for a Logic Design Engineer.
You will work on high-speed digital design and is targeted towards low power optimized implementations of high speed IPs.
Your responsibilities will include but are not limited to implementing RTL in System Verilog, validating the design, synthesizing the design and closing timing.
You will also have an opportunity to work on high-level understanding of the architecture through to the details of timing, and will contribute to specifications at multiple levels, including the HAS and MAS microarchitecture spec.
You must be able to balance design trade-offs with modularity, scalability, DFX requirements, power, area, and performance.
The ideal candidate should exhibit behavioral traits that indicate excellent written and verbal communication skills, as they are critical on a small, fast-moving team.
As part of a growing, dynamic new business, the candidate must also be successful working with a small team and manage multiple tasks and changing requirements in an innovative environment.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.
US, California, Santa Clara