Develops preSilicon functional validation tests to verify system will meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing.In this position, you will be responsible for being a member of a team of verification engineers to verify and deliver world class intellectual property IP to various business groups within Intel. Tasks include writing test plans for functional coverage, defining the architecture of test benches, developing verification methodologies and mentoring verification engineers in the team.
You should possess a Bachelor's and/or a Master's degree in Electronics and/or Electronics and Communication and/or Very Large Scale Integration VLSI area. Additional qualifications include: More than 8 years of VLSI Front-end experience Sound understanding of functional verification fundamentals encompassing state machine verification, complex protocol verification, functional test strategies, directed and stress test generation, verification infrastructures and verification and/or debug flows simulations Adept Gate level in programming and/or scripting C++, Perl* and others and be conversant with flows and tools for VLSI logic design and/or functional verification The following qualifications would be added advantages: In depth knowledge of System Verilog and verification methodologies like OVM Working experience on the PCIe, SATA, OCP, UARTWorking knowledge of modern PC architecture Specific IO architecture knowledge is a plus Extensive knowledge of System Verilog and working knowledge of verification methodologies like OVM and othersInside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.