Job Description Performs logic design, Register Transfer Level RTL coding, and simulation to develop functional units pertaining to High Speed Serial IOs for Mixed-Signal IP group MIG, Bangalore. Understands the High-level Architectural spec/Standards pertaining to PCIe, MIPI, SATA, MIPI, Display PHY layer and generate micro-architectural spec and RTL design. Simulates the functional units, takes it through extensive front-end quality checks, integrates it along with Analog models to build PHY family and packages it to deliver to Subsystem & SoC teams. Works with Structural Design team to close back-end implementation aspects such as floor-planning, area & timing. The role requires extensive collaboration with adjacent functional teams such as pre-silicon validation, Analog design, structural design, DFT design, post-Silicon within MIG and also with Subsystem SoC teams.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.