Optimization of power consumption in ET Digital Signal Processing DSP with focus on digital filters.
Power consumption is one of the most critical Key Performance Indicators KPI's in mobile communication. The rapidly increasing requirement for higher throughput makes it more difficult to keep the power consumption low, which is important for a better user experience. The purpose of this thesis is to analyse and to optimize given digital filters in the ET DSP with respect to filter order and chosen structure towards a lower power consumption.
A major task is the expansion of the filter structure to parallel processing enabling a sample rate that is higher than a given system clock rate. A major task is the comparison between different filter topologies IIR, FIR, ... and subsequent down-selection meeting predefined criteria. After the analysis the filters shall be implemented as bit-true model in SystemC.
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