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Job ID: JR0048274
Job Category: Intern/Student
Primary Location: Munich, DE
Other Locations:
Job Type: Intern

Student for internship (f/m) - Implementation of an automation tool for RTL processing

Job Description

To further enhance and optimize our digital design flow, we are looking for an intern who implements an automation tool for processing RTL design code written in a Hardware Description Language VHDL or SystemVerilog.


A qualified candidate would need to have the following skills:

  • Program development in an object-oriented programming language C/C++, Java, Python
  • Profound understanding of RTL digital design using HDLs
  • In-depth understanding in the semantics of VHDL and SystemVerilog
  • Experience in working in a UNIX environment and using scripting languages Perl, TCL
  • Good knowledge in language parsing and compiler development.
  • Experience with digital design synthesis and formal equivalence checking.
  • Good communication skills in English.

We expect the candidate to be on site at least once a week to frequently review the progress and fine-tune the technical alignment.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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