To further enhance and optimize our digital design flow, we are looking for an intern who implements an automation tool for processing RTL design code written in a Hardware Description Language VHDL or SystemVerilog.
A qualified candidate would need to have the following skills:
We expect the candidate to be on site at least once a week to frequently review the progress and fine-tune the technical alignment.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.