-Develops preSilicon functional validation tests to verify system will meet design requirements.
-Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests.
-Analyzes and uses results to modify testing.
We are looking for B. Eng or M. Eng in Electronics, Computer or Electrical Engineering graduates who have 5+ years of design verification exposure and experience.
We would like someone with:
-Expertise in standard verification flows and processes, including constraint random verification, testplan, BFM, verification infrastructure, test cases and functional coverage development.
-Proficiency in OVM, UVM or VMM methodologies.
-Experience in verifying complex, multi-clock and multi-power domain designs.
-An ability to collaborate with a diverse team in a dynamic work environment.
-Protocol knowledge in I/O specifications such as USB2, USB3, SATA, PCIe.
-A love of problem solving and the motivation to stress test design with the goal of finding all possible design bugs.
-An ability to comprehend design specifications and documentation and distill the information into a comprehensive testplan and validation strategy.
-Working level mastery of Unix based design environment, industry standard digital design tools, scripting languages and ASIC flows.
The candidate should also be:
-A fluent communicator in both verbal and written forms.
-An independent, motivated team player with leadership qualities.
-Able to drive/influence issue resolution and proficient in stakeholder management.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.