Digital Design Engineers are responsible for the design and development of electronic components. This position is for a Senior Staff Structural/Physical Design Engineer in the Mixed Signal IP Solutions Group's (MIG) Structural Design team. We are seeking an individual who has technical expertise in the RTL to GDSII phase of the ASIC design flow and has previously played a leadership technical leading role in development and delivery of leading edge physical databases for ASICs, SoCs or IPs.
A successful candidate should be proficient in aspects of physical design from RTL hand-off through streaming out a clean GDSII (such as Floorplan, Synthesis, Auto Place & Route, Signal Integrity Verification, Clock Tree Synthesis, Performance Verification, Reliability Verification, Power Analysis & Optimization, Timing Closure etc). The candidate must be a technical content expert in at least one of the above mentioned structural/physical design areas or he/she must have led technical teams for multiple IP and/or SoC deliverables.
The candidate must be able to interact effectively with cross functional design engineers/leads as well as communicate effectively with management and peers. In addition, be self-motivated with the initiative to seek constant improvements in the physical design methodologies. The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. The candidate must be able develop training programs & mentor junior design engineers.
You should possess a relevant educational qualification, BSEE or equivalent with 7+ years/MSEE or equivalent with 6+ years design experience in the structural/physical design domain.
Additional qualifications include:
- Extensive knowledge & hands-on experience in VLSI structural/physical design methodology, flows and relevant EDA tools.
- Experience in leading technical teams in the delivery of Hard IP and/or SoC products.
- Hands-on expertise with scripting languages such as Perl, TCL, and knowledge of hardware description languages of VHDL & Verilog.
- Experience of mentoring junior team members and charting their development for success.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.