As a Pre/Post Silicon HVM Testing Development HTD engineer, you are required to define, create, and develop HVM reset, TAP and DFx fabric tests cases for validating the HVM used model on the RTL simulation and emulation environment, also ensuring all the Design/DFx features are meeting the required HVM specs.
You are responsible for the development of methodologies, execution of validation plans, and debug of failures. Requires broad understanding of HVM testing areas and requires interfaces with Architecture, Design, and Pre and Post-silicon content teams in enabling test content and providing feedback for debug features.
Good understanding and experience in any of the following architecture: Reset, TAP, CPU computer architecture & etc.
Possess strong problem solving, analytical and debug skills.
Good team works and able to work with multiple key stakeholders
Has background on computer architecture and Perl/Python programming is a plus
Has SW/HW testing eg: tester is a plus
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.