In this position, you will be leading a Mixed Signal IP project design team within which consists of circuit designers, RTL designers, structural designers, mask designers, signal integrity and power delivery engineers. The design team is responsible for developing a given hard IP [e.g. USB2, 8Gps IO, Audio/Soundwire IO, GPIO] to deliver to the SoC customers.
Your responsibilities include but not limited to:
Planning the project resource, schedule and execution managing and removing road block in the project execution to meet the agreed schedule SoC, stakeholder management, customer communication and change request disposition. Often, you may need to work with the micro-architects to identify best solution to technical issues e.g. bug fixes and also work with the structural and mask design leads on schedule mitigation.
BSc or MSc in Electronics/Computer engineering with at least 8 years involvement in IP or platform design with 2 year in leading a project. The candidate should have strong inter-personal skills, good with organization and planning, be able to work independently and excel in stakeholder management.
Any relevant amount of experience would be an added advantage, including:
- IP integration experience involving various disciplines e.g. circuit, RTL, APR and custom layout.
- Strong background in analog IO interface design including platform design implementation of various IO interfaces.
- Strong analytical and problem solving skill.
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.