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Job ID: JR0043740
Job Category: Engineering
Primary Location: Munich, DE
Other Locations:
Job Type: College Grad

Physical Design Engineer Layout Engineer m/f

Job Description

Creates bottoms-up elements of chip design including but not limited to FET, cell, and block-level custom layouts, abstract view generation, RC extraction and schematic-to-layout verification and debug using phases of physical design development including parasitic extraction, polygon editing, auto-place and route algorithms, floor planning, full-chip assembly, packaging, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design.In this position you will work hands-on layout and verification of CMOS circuit blocks such as Power-Management ICs, DCDC Converter, mixers, amplifiers, PLLs, ADC/DACs, filters and dedicated analog processing circuits. As a PMIC Analog f/m you shall transfer circuits into photo masks using Cadence/Virtuoso, perform verifications using Mentor/Calibre and mixed signal. The translation and verification of this schematics require profound knowledge of semiconductor circuits as well as know-how in modern semiconductor technologies


Inside this Business Group

Intel is a leading provider for technologies that support wireless and handheld computing devices. The Wireless Communications and Computing group develops essential technologies, architectures and building blocks to support advanced processing, communications and memory aspects of both personal digital assistants (PDAs) and wireless handsets.

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