Primary responsibilities of a Design Quality and Reliability Tech Lead is guiding a team of engineers in the areas of design, verification and execution of simulations as well as developing new design methods, flows and tools in IP and SOC VLSI circuit projects with the focus on the quality and reliability Q&R aspect of the design. Primary responsibilities will be establishing technical leadership within a team of engineers and lead overall partnership with design teams in Hard IPs and SOCs to meet Q&R design challenges.Key tasks include project management, providing technical guidance to more junior team members and executing pre-silicon design modeling, correct-by-construction, simulation, verification tasks to mitigate Device Aging, Interconnect Reliability, ESD Electro Static Discharge, LU Latch Up, SER Soft Error Reliability and design/package interaction. Other responsibilities include performing risk assessment for pre-silicon design reliability issues and analysis of PV and circuit marginality data.
MSEE with 5-10 years of experiences in circuit simulation/PV/RV/Physical Design or PHD EE with relevant experience of 3-5 Years is required. Experience in component design, VLSI tools, flows, methods for silicon design and having worked through silicon chip design development cycles. Knowledge of the Quality & Reliability aspects of a VLSI design, awareness of the respective implications of Q&R requirements to the circuit design are required. Experience in project management and overall knowledge of VLSI design flow, technology development and device physics are required.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.