Job Description Performs logic design, Register Transfer Level RTL coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs. Participates in the development of Architecture and Microarchitecture specifications for the Logic components. Provides IP integration support to SoC customers and represents RTL team.As an RTL engineer you will own or participate in the following: -RTL Development: development, assessment and refinement of RTL design to target power, performance, area and timing goals. -Validation: support test bench development and simulation for functional and performance verification. -Performance exploration and correlation: explore high performance strategies and validate that the RTL design meets targeted performance. -Design delivery: work with cross-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power.
BSEE/MSEE is required-The ideal candidate should possess an BS or MS in Computer or Electrical Engineering with 2+ years of RTL experience.-Knowledge in one or more of the belowKnowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools.Knowledge of logic design principles along with timing and power implications.Understanding of low power & high performance microarchitecture techniques.Experience using an interpretive language such as Python, Ruby, Perl or TCL.Education
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.