As an experienced FPGA Engineer at MVE you will have a meaningful effect on the next generation logic designs, working shoulder to shoulder with the Design and Architecture teams.
In this role you will create emulation/Field Programmable Gate Array FPGA models from a Register Transfer Level RTL design using emulation/FPGA synthesis, partitioning and routing tools.
Defines and documents RTL changes required for emulation/FPGA.
Develop hardware and software collaterals and integrates it with the emulation/FPGA model. Test and debug the emulation/FPGA model and collaterals.
Define and develop new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for PreSilicon and PostSilicon functional validation as well as SW development/validation.
Develop improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform.
Interface with and provides guidance to presilicon Validation teams for optimizing preSi validation environments, test suites and methodologies for emulation efficiency.
Develop and apply automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization.
BSC/MSC in electronic/computer engineering.
7+ years of experience in RTL design, simulation, synthesis, FPGA prototyping.
Proactive approach and ability to lead projects
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.