Join Intel as part of the Mixed Signal IP group - MIG in Bangalore. In this position you will be responsible for developing, proving & implementing DFT solutions for High Speed Serial IOs & Display PHYs. You will be responsible to enable and ensure that IPs meet aggressive DFT coverage requirements set by SoCs. The position involves close collaboration with pre-silicon and post-silicon teams within MIG and also with SoC DFT teams to ensure robust integration & validation and hitting the required coverage goals. The person should be able to mentor/groom junior people in the team.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.