Job Description The candidate will be part of graphics DFX team under Visual Technologies Teams VTT responsible for delivery of DFX features and scan test content for graphics IPs developed for Intel's CPUs/ SOCs . In this position, the candidate will primarily work on DFT design/implementation and/or ATPG for Intel's next generation graphics cores. Responsibilities include but not limited to:1.ATPG , DRC analysis , coverage-analysis at partition and sections levels.2.Validation of scan content through gate-level simulation .3.Work with structural design teams for ATPG input collaterals,timing closure and coverage improvement.4.Development of scan content generation/validation flows .5.Support post-silicon validation teams for content enablement on ATE & yield-improvement6.Development of micro-architecture, RTL coding and validation of DFX units
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.