In this position, the candidate will be responsible for the microarchitecture and design of soft IP cores for Intel's next generation chips including SOCs for the different market segments.
Qualification : Master of Science or a Master of Technology degree in Electrical Engineering with more than six years of relevant industry experience or a Bachelor of Science Bachelor of Technology degree in Electrical Engineering with more than eight years of relevant industry experience. Experience : Relevant ASIC design/validation experience in front end processes including RTL development, functional and performance verificationExpertise in design, development and integration of design blocks IP for system-on-chip SoC componentsExpertise in verilog and system verilog based logic designExperience in all design tools like linting, DC, CDC, LECExperience in one/more of the following areas PCI_Express, USB, SATA, SDIO,MIPI and /or AMBA standards OCP, AXI, AHB etc..Knowledge of SVAKnowledge of considerations for performance, power and cost optimization is desirableInside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.