As a Senior Validation Engineer, you will be part of the Xeon Server Functional Validation group which comprises of several validation teams including Integrated I/O, Memory, Power Management, RAS, Security, and Mesh. The Senior Validation Engineer will be responsible for:
Validating multiple CPU I/O designs, including PCIE and UPI, in emulation and post silicon.
Creating validation plans, executing that plan, and debugging or root causing failures found from the plan.
Must be comfortable working in team setting as it requires interfacing with architecture, design, pre-silicon, and validation teams.
Bachelor's or a Master's Degree in Computer Engineering, Electrical Engineering, Computer Science or equivalent
5+ years of experience in microprocessor validation or QA environment
CPU micro-architecture and high speed bus protocol knowledge
Strong debug skills and ability to solve complex problems
Be able to demonstrate success in communicating plans, status, issues, concerns
Experience with PCIE and/or UPI protocols
Validation experience with high speed serial protocols
Familiarity with emulation environment and tools, and Logic or Protocol Analyzer equipment
Python Scripting Experience
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.