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Job ID: JR0046692
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

Front End Design Automation Engineer

Job Description

The position is for a senior FE design automation and methodology expert in the area of RTL design and/or validation. You will be part of a FE design methodology team that is leading and driving industry leading design solutions and methodology for all designs at Intel. Your role will involve evolving design systems to improve reliability and velocity through methodology, automation, development, operation and refinement. Job qualification:In depth technical expertise and operational skills in RTL IP to SoC integration, IP hand-off, RTL quality sign-off lint, constraints etc., RTL hand-off to SD and/or pre-si validation. Proven track record of driving methodology/innovation in the above mentioned areas towards reduced cost, improved TTM and overall competitiveness of the designs. Must possess excellent stakeholder management & communication skills. Knowledge of languages like Perl, Python, shell and Verilog, System Verilog is a plus. Following skills are a must have depending on your area of expertise: RTL model build & releaseo Software build, release & deployment management, continuous integration tools and frameworks. o Deep understanding of SCM, build & release processes for agile and dynamic environment. IP hand-offo Expert understanding of design collateral and quality sign-off requirements for IP hand-offo Thorough understanding of IP ecosystem from packaging & release on the IP to download and quality sign-off on SoC side. IP - SoC integrationo Expert understanding and knowledge in the SoC globals, fabrics and relevant architecture detailso Deep technical knowledge in different needs and challenges of IP integration at SoC as well as exposure to different SoC integration methodologies RTL quality and sign-offo Leadership experience in driving RTL quality closureo Expert understanding of methodology across CDC, RDC, low power, DFT and constraints RTL hand-off to SDo Expertise in synthesis, timing analysis and timing optimized netlist generation. o Must have worked on latest UPF technologies and understand the various Power collaterals needed to synthesize design. o Must possess working knowledge of constraints and handling Power intent. Pre-Si validationo Expertise in testbench methodology and entire spectrum of verification management solutionso Experience of working with industry leading RTL simulatorsWe want to speak with you if: You architect, design, and deliver methodology solutions. You are responsible for rapid and accurate resolution of technical challenges, lead flawless implementations and integration of custom features. You excel at customer service, leadership and interface skills. You possess a can-do attitude, are driven by research, problem-solving, and thrive on challenges.


Qualifications

Qualifications :

BE/M.Tech

12-15 Yrs of Experiecne

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


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