Sr. NAND Layout Architect and Pathfinding Engineer
Responsibilities include large-scale block layout, complex layout blocks, small to medium scope section lead, small to medium scope layout projects with mentorship and guidance, development or improvement projects, tool evaluations, etc.
Lead, coordinate, facilitate and monitor the daily activities of a small to large group of support resources within their section or project team while holding a leadership role
Able to contribute to the layout execution at a prominent level.
With minimal supervision, prioritizes workload to successfully manage multiple tasks and responsibilities concurrently. With minimal supervision, manages daily operations within their assignments, showing appropriate consideration for established project objectives and standard project methodologies.
With minimal supervision drives high level layout execution on moderately complex blocks. Given established boundary conditions and constraints, develops detailed task lists, forecasts resource requirements, and creates long range schedules for sections and small projects.
Frequently involved in developing the skills of less experienced layout designers through formal training, coaching or mentoring.
Proactively addresses and communicates issues impacting productivity and works to resolve those roadblocks.Creates bottoms up elements of chip design including but not limited to FET, cell, and blocklevel custom layouts, FUBlevel floor plans, abstract view generation, RC extraction and schematic
Tolayout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, autoplace and route algorithms, floor planning, fullchip assembly, packaging, and verification.
Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.
Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments.
Requires expansive knowledge and practical application of methodologies and physical design.
15 years or more with Non-Volatile Memory Layout
Typically performs as a highly proficient technical individual contributor or specialist on complex layout and leadership assignments.
Sufficient Layout Industry Experience to lead Architecture Pathfinding initiatives NAND Layout Focus
Candidate will have at least 10-15 years of direct layout experience.
Candidate will have a good understanding of layout tools / methodologies.
Experience of basic electronic circuit functionality and behaviors passive and active circuit structures.
Knowledge of CMOS and VLSI component design principles.
Highly proficient with industry based CAD layout tools including: Cadence Virtuoso, VXL. Strong background in verification Calibre DRC, LVS and others.
Strong engineering problem solving and analytical skills Strong verbal and written communication skills
2+ year technical degree in VLSI or Physical Design/Mask Design.
Layout section/FUB lead experienceAbility to lead and work well in a team environment. Experience with layout of the standard cells for APR, custom standard cell library, scribe layouts, and runset regression test cases.
Knowledge in analog design and layout guidelines, high speed IO, matching devices, symmetrical layout, signal shielding, other analog specific guidelines Ability to accomplish the activities with high quality, minimal supervision, and on time delivery.
Experienced with UNIX, as well as MS Windows and web based tools.
Inside this Business Group
Non-Volatile Solutions Memory Group: The Non-Volatile Memory Solutions Group is a worldwide organization that delivers NAND flash memory products for use in Solid State Drives (SSDs), portable memory storage devices, digital camera memory cards, and other devices. The group is responsible for NVM technology design and development, complete Solid State Drive (SSD) system hardware and firmware development, as well as wafer and SSD manufacturing.