- This staff engineer position is to be part of the Malaysia Design Center MDC newly extended charter under IP Validation Center of Excellence organization in Penang.
- Responsibility includes developing capabilities on pre-silicon environment in FPGA, model build/compilation, establishing FPGA simulation and enabling the use of early prototyping platform across RTL validation, PHY development and power/performance validation.
- The candidate will also be responsible for supporting RTL and IP debug on this early prototyping platform. The successful candidate must be able to lead forum involving cross functional teams such as Design, Validation, and external vendors.
- This position offers a broad exposure to system architecture, IP design/validation methodologies, and FPGA/emulation technologies.
- Bachelors/Masters/PhD in Computer Science/Electrical/Electronic Engineering with at least 6 - 8 years of technical experience.
- Knowledge in C/C++, SystemVerilog, RTL, Python, IA, SoC Architecture, UPF and Low Power Flows
- Understanding of simulation, synthesis and timing analysis flow with involvement in at least one SoC/sub-system design tape-out.
- Hands-on experience in silicon/FPGA debug, RTL validation or Power/Performance validation is a plus.
- Experience in Emulation, Altera/Xilinx/Synopsys/Mentor/Cadence Tools Flow, HAPS is a plus.
- Should have strong communication, analytical skill and a good team player.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.