Job Description Primary responsibilities of design quality and reliability engineers Q&R is in design, verification and execution of simulations as well as developing new design methods, flows and tools in IP and SOC VLSI circuit projects. Key tasks include executing pre-silicon design modeling, correct-by-construction, simulation, design verification tasks to mitigate circuit Device Aging, Interconnect Reliability Electromigration, ESD Electro Static Discharge, LU Latch Up, SER Soft Error Reliability and design/package interaction. Other responsibilities include performing risk assessment for pre-silicon design reliability issues and analysis of PV and circuit marginality data.
MSEE with 2 Years of experience in circuit simulation/PV/RV/Physical Design and with related college courses and projects required. Skills in device physics/circuit operations as well as strong skills in technical problem solving, communication and data analysis needed. Knowledge in design methodology timing, noise, physical circuit design, layout needed as well as understanding/optimizing performance/reliability/power tradeoffs. Experiences in overall knowledge of VLSI design flow, technology development and device physics are a plus.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.