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Job ID: JR0041738
Job Category: Intern/Student
Primary Location: Penang, PNG MY
Other Locations:
Job Type: Intern

Graduate Trainee

Job Description

Job Description: Creates analog layout bottoms-up elements of chip design including FET, cell, and block-level custom layouts, analog floor plans, and schematic-to-layout verification. Analog layout debugging including RC extraction, Design Rule check, and Electro Static Discharge.


Qualifications

Bachelors of Engineering Degree

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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