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Job ID: JR0045349
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations:
Job Type: Experienced Hire

Senior SoC DFX Engineer

Job Description
  • Defining DFX methodology for large SOC chips, implementation and verification.
  • Working in collaboration with design, implementation and other teams to ensure DFX are implementable.
  • You will also understand that relationships formed with other peers, teams, and organizations is key to success in SoC, package and system level test.

Direct Responsibilities:

  • Lead DFX architecture, design, implementation and verification on SOC.
  • Define design schedule for DFX features.
  • Work with DV team to enhance DV environment for DFX verification and validation.
  • Work with implementation team to develop timing constraints for DFX logic.
  • Developing working relationship with operation team to generate tester vectors.
  • Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results.
  • Interact and drive vendor relationships to support development.

The ideal candidate will be able to demonstrate the following behaviors:

  • Ability to work effectively with both internal and external teams & customers is expected.
  • Ability to mentor other engineers and technically guide them.
  • Provide technical direction for other team members.
  • Experience with silicon which include processor cores and custom logic working together.
  • Strong problem solving/leadership skills.
  • Strong written and verbal communication skills.
  • Facilitator of direct and open communication, diversity of opinion, and debate.


Qualifications

Minimum Requirements:

  • BS degree in Electrical Engineering, Computer Engineering or other related field of study with a minimum of 10+ years of relevant experience in SOC/system design/verification or MS degree with 8+ years or PHD with 6+ years of directly related experience with SOC/Package/Board debug and test.

Candidates must have the following:

Lead DFX implementation on complex SOC

Deep understanding of the following DFT features:

  • Scan design implementation and validation
  • ATPG compression scheme: TestKompress, DFTMAX Ultra, Optmizer
  • MBIST design, implementation and verification
  • High Speed IO Test
  • All aspects of boundary scan
  • LBIST design and validation.

  • Proven expertise in debug and test of silicon based products.
  • Must have gone through complete process and generating and debug of test vectors on a tester.
  • Extensive experience with designing/dealing with manufacturing test requirements.
  • The ability to work as an individual and as part of a team to deliver a product which is debug and test friendly starting from the creation of the spec, design, verification, and finally to productization.
  • Expertise in dealing with and designing complex IP's from different sources onto the same piece of silicon understanding debug and test requirements.
  • Understand system and package implications of the silicon design decisions.

Preferred Skills:

  • Experience with Mentor BIST and SCAN insertion tools or equivalent.
  • Experience with design for test and debug, at Silicon, Multichip package and Board level
  • Experience with board design/debug and challenges

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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