The candidate will be responsible for delivering pre-Si validation models to all the stakeholders like, functional validation, backend, emulation and driver team for graphics chips. It involves understanding of overall design architecture and floorplan, flows and methodologies and validation environment. The candidate has to interact with multiple stakeholders on regular basis, understand their requirement and proactively look for solution. This job also involves bringing efficiency and methodology improvements for improving the TPT.
4yrs-10yrs RTL Integration/validation expertise. The candidate should possess Masters degree in electronics/computer * Experience in pre-silicon validation tools and methodologies* Good understanding of design methodologies, Verilog and high level SD flows * Strong background in RTL based emulation platforms development and usage* Strong background in any of the industry standard emulation tools and flows* Expertise in Integrating and Verifying complex SoC * Expert understanding of product verification techniques using emulation * Demonstrated experience in a large, complex, global organization-ability to effectively work and communicate across organizational lines * Strong written, presentation, and oral communication skills for technical and non-technical audiencesExpertise in reading design spec docs, define test plans and write test cases in high level languages Python, PerlExpertise at triage and debug of HW failures at simulation and emulation environmentsAbility to work independently with designers, micro-archs to drive closure of issues found during testingFamiliar with DX, OGL, OCL specs would be added advantageGFX knowledge is not mandatory but plus.Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.