Job Description Develops preSilicon functional validation tests to verify system will meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing.Leading major cluster/top level verification, developing test environment, verification specification documentation and working with cross-functional engineering teams on architecture, design and verification.As a Senior verification engineer owning the verification of a certain area of functionality in an IPU design. Work closely with architecture and RTL designers on verifying the functionality correctness of the design, Develop test plans and test environments Develop tests in assembly, C, or SV according to test plans, Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered
BS, MS in Electrical Engineering, Computer Science, or Computer Engineering is required.-The candidate should have 7+ years of verification experience.-In-depth knowledge of digital logic design, chip architecture and microarchitecture.-Experience in developing testplans/testbenches, C-based transactors, and writing/debugging assembly based tests.-Experience with advanced verification techniques such as formal and assertions a plus.-Experience in silicon bringup a plus.-Experience in C or C++ programming a plus-Experience using an interpretive language such as Perl, Python or Ruby.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.