As a member of the ASIC Frontend Design and Integration team, you will be part of Intel's Programmable Solution Group PSG, working on complex ASIC and FPGA designs in leading edge process nodes.
Responsibilities include the following:
Integration of complex IP's, which requires in-depth knowledge of the IP. Tasks include authoring detailed functional spec, microarchitecture spec, developing surrounding logic, integration and optimization of any memories and hard macros required, and writing timing constraints.
RTL and constraint quality checks, including lint, CDC, Fishtail.* Contribute to chip-level integration: interface definition, clock/reset architecture, RTL, timing constraints integration
Development, assessment, and refinement of RTL design to target power, performance, area and timing goals.
Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis.
Support IP, subsystem, and full-chip level verification by providing design requirements, review verification plan, functional/code coverage results, and simulation debug
Power state definition and management Dynamic clocking solutions Clock generation and asynchronous clock crossing strategies
Work with Chip Architecture, Design Verification, Physical Design, DFT, and power teams to achieve first tapeout success on designs
Work with cross-functional teams to make sure designs are delivered on time, and with highest quality, by incorporating proper checks at every stage of the design process.
BS or MS in electrical engineering or computer science
5+ years of experience in high performance digital logic designs and integration
2+ years of experience with synthesis, static timing analysis