Creates bottomsup elements of chip design including but not limited to FET, cell, and block level semi custom layouts, floor plans, abstract view generation, RC extraction and schematictolayout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, auto place and route algorithms, floor planning, full chip assembly, packaging, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design.
Bachelors/Masters in Electronics Engineering /Computer Science or equivalentVery good understanding of VLSI design flow flow. Experience in Physical design methodologies and sub-micron technology.ICC/ICC2 Place & Route Timing Constraints / STA PrimeTime, EM/IR-Drop/Xtalk analysis PT-SI, Apache, LEC formal verification, MVRC or VC-LP low power Verification, CalibrePhysical verification DRC/LVS/Antenna.Tcl/Tk/Perl to automate design process and improve efficiency.Synopsys suite IC Compiler, Primetime, Design CompilerInside this Business Group
Communication & Devices Group: The wireless revolution at Intel! We are one team - passionate engineers and technologists from diverse industry backgrounds working together to realize a world of connected computing. We are bringing the best ideas from the brightest minds to deliver future mobile experiences into the market. We are on the journey towards making Intel a wireless leader with exciting products for the Internet of Things, 5G and an opportunity to change the world with your work.