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Job ID: JR0045017
Job Category: Contract Employee
Primary Location: Folsom, CA US
Other Locations: California, Santa Clara;
Job Type: Intel Contract Employee

Sr. NAND Layout Architecture and Pathfinding + C

Job Description

Leadership:

  • Performs proficiently as a leader, facilitator, or technical mentor on various types of complex projects and programs
  • Demonstrates appropriate consideration for established project objectives, standard project methodologies and all project boundary conditions
  • Can direct and support resources, team members or program participants in the coordination of daily project operations
  • Contributes to project-level activities (e.g. strategy, design priorities, goal setting, and productivity/methodology enhancements)
  • With little supervision, manages daily operations and creates and maintains detailed schedules, prioritizes workload to successfully manage multiple tasks, resources and responsibilities concurrently
  • Communicates effectively with project stakeholders (Layout management, design engineering, design automation)
  • Sets team and individual expectations related to project execution
  • Proactively addresses and communicates issues impacting productivity and works to resolve those roadblocks

Technical Expertise:

  • Performs as a high-level individual contributor using expert technical knowledge, extensive experience and a well-developed network of resources and contacts to complete highly complex assignments
  • -Independently drives high level layout execution on large-scale, complex layout projects, complex development or improvement projects, working groups, training programs, tool evaluations, etc.
  • Plans, draws, assembles and verifies highly complex blocks, sections or fullchip designs
  • Recognized as an expert in layout tools (Virtuoso/Calibre)


Process Improvement:

  • Independently identifies and solves difficult problems and develops recommendations for improvements that impact the future direction of projects, tools and methodologies
  • Within area of expertise; independently expands work beyond the explicit instructions provided, frequently improving upon the anticipated results or increasing the impact
  • Recognizes the need for new or improved automation to enhance processes
  • Develops and tests the new automation and follows the necessary steps for implementation
  • Can work with technology partners to drive change to facilitate innovative layout designs
  • Regularly contributes or creates training material to present on new or updated layout methodologies, technology changes or tool enhancements


Qualifications

Education:

2 year technical degree in VLSI or Physical Design/Mask Design

Minimum Qualifications: 

  • 5 years experience of basic electronic circuit functionality and behaviors (passive and active circuit structures)
  • 5 years’ of CMOS and (VLSI) component design principles
  • 5 years’ experience with industry based (CAD) layout tools including: Cadence (Virtuoso, VXL)
  • 5 years’ experience with industry based verification tools (Calibre DRC, LVS and others)
  • 5 years’ experience in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines) 
  • 5 years’ experience with UNIX, as well as MS Windows and web based tools

Preferred Qualifications:

  • Preferred 8+ years of direct layout experience
  • Strong engineering problem solving and analytical skills 
  • Strong verbal and written communication skills 
  • Layout section/FUB lead experience
  • Ability to not only work well in a team environment, but to add positively to the team
  • Expert in tight pitch, highly sensitive layouts (mirrored/stepped)
  • Word-line and Bitline decoder layout using various metal stacks
  • Dual/Quad pitch socket interfaces (2D/3D)
  • Developing process limited designs
  • Extensive experience in building memory arrays from the ground, up
  • 6T or 8T bitcell SRAM layout
  • Experience in pathfinding activities for future process nodes
  • Experience with 3D architecture
  • High/Low voltage layout integration

Inside this Business Group

Non-Volatile Solutions Memory Group:  The Non-Volatile Memory Solutions Group is a worldwide organization that delivers NAND flash memory products for use in Solid State Drives (SSDs), portable memory storage devices, digital camera memory cards, and other devices.  The group is responsible for NVM technology design and development, complete Solid State Drive (SSD) system hardware and firmware development, as well as wafer and SSD manufacturing.



Other Locations

California, Santa Clara;


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

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